The invention relates to electrically erasable and programmable memories, and more particularly, to a flash memory that is erasable by page.
The market for electrically erasable and programmable integrated circuits comprises essentially EEPROM memories and FLASH (or FLASH-EEPROM) memories. EEPROM memories may be of the programmable type erasable by word or the programmable type erasable by page. Due to the current technology, FLASH (or FLASH-EEPROM) memories are usually programmable by a word and erasable by a sector. A sector usually contains a large number of pages.
FIG. 1 diagrammatically shows a FLASH memory array including a plurality of memory cells CFi,j laid out in matrix fashion and connected to word lines WLi and bit lines BLj. The memory cells CFi,j in the FLASH memory have a very straightforward structure and comprise only a floating gate transistor FGT. In this case an NMOS transistor with its gate G connected to a word line WLi, its drain D connected to a bit line BLj and its source S connected to a source line SLi. The bit lines BLj are grouped in columns of rank k to form binary words Wi,k, for example, each including eight cells VFi,j (bytes). The cells in a particular word Wi,k may be adjacent (as shown in FIG. 1) or they may be interlaced with cells belonging to other words. A physical page Pi in the FLASH memory is formed by the set of memory cells Ci,j connected to the same word line WLi, and thus comprises a plurality of binary words Wi,k. A sector is formed by a set of pages Pi, in which the source lines SLi are interconnected and are always at the same electrical potential.
In this type of FLASH memory, programming of a cell includes injecting electrical charges into the floating gate by a xe2x80x9chot electron injectionxe2x80x9d effect, while erasing a cell includes extracting electrical charges trapped in the floating gate by the tunnel effect. An erased FGT transistor has a positive threshold voltage VT1 with a low value, and a programmed transistor has a threshold voltage VT2 greater than VT1. When a read voltage VREAD between VT1 and VT2 is applied to its gate, an erased transistor will be conducting, which by convention corresponds to reading a logical 1. A programmed transistor will remain blocked, which by convention corresponds to reading a logical 0.
Due to the simplicity of their memory cells which do not include any access transistors as in EEPROM memories, FLASH memories have the advantage of being very compact in terms of the area of occupied silicon and thus, for the same silicon area, have a significantly greater storage capacity than EEPROM memories at a lower cost. On the other hand, they are less flexible in use due to the need to simultaneously erase all memory cells in the same sector.
However, some applications benefit from the advantages of FLASH memories (compactness and low cost) while benefiting from the possibility of erasing by page, for example, when the volume of data to be recorded is small and it would be impossible to erase an entire sector before programming a page. However, there are some difficulties for a FLASH memory erasable by page.
To understand the problem that arises, it is important to first remember that a memory cell can be erased using the source erase method, or the channel erase method.
The source erase method shown in FIG. 1 includes applying a positive erasing voltage VER+ on the order of 4 to 5 V to all source lines SLi in the same sector, while the word lines WLi in the sector considered receive a negative erase voltage VERxe2x88x92 on the order of xe2x88x928 V. The material forming the transistor channel (substrate or well) is grounded. The voltage difference that exists between the source S and the gate G of the transistors has the effect of tearing off electrical charge trapped in the floating gates (by the tunnel effect) and erasing the transistors. The negative voltage VERxe2x88x92 is applied to the gates of all transistors in the same sector by inhibiting a word line decoder XDEC (FIG. 1). The voltage VERxe2x88x92 is applied to the input of this decoder, and the decoder then applies this voltage to all word lines WLi in the sector to be erased regardless of the address received at the input. At the same time, the impedance of all outputs from a column decoder YDEC connected to bit lines BLj is set to a high level.
Channel erasing is different from source erasing in that the positive erasing voltage VER+ is applied to the transistor sources through the material forming the channel regions (substrate or well) to which a biasing voltage VB is applied. The PN junctions that exist between the channel regions and the source regions are biased to make them conducting, and the voltage VB is applied to all transistor sources in the same sector to form the voltage VER+. At the same time, the negative erase voltage VERxe2x88x92, as before, is applied to the gates of transistors through the word line decoder XDEC that is in the inhibited state.
The advantage of channel erasing is that the channel regions and source regions are at approximately the same electrical potential, since channel/source junction diodes are biased to make them conducting. Therefore, compared with source erasing, there is no more leakage current in the source/channel direction. The erase voltage VER+ may be increased to a higher potential than in the case of source erasing, for example, 8 to 10 V compared with 4 to 5 V in the first case.
One known approach for making a FLASH memory erasable by page includes providing a selection transistor for each source line SLi capable of selectively applying the programming voltage VER+. This type of approach is in line with the information disclosed in patent EP 704,851 and application WO 98/33187, in which a word is selectively erased by equipping cells of a single word of a source selection transistor.
However, this approach has a number of disadvantages. First, a FLASH memory cell is programmed with a non-negligible drain-source current. Consequently, if all cells in a word are programmed simultaneously, a high current is collected by the source line selection transistor. This current increases the drain-source voltage of the selection transistor, and there is a corresponding reduction in the drain-source voltage of the floating gate transistors, and an increase in the programming time. Therefore, the cells in a same word must be programmed individually, or at the same time as cells belonging to other binary words (WO 98/33187).
Furthermore, the use of source line selection transistors is not compatible with the channel erase method. The erase voltage VERxe2x88x92 in this case is applied through the material forming the channel. Consequently, the use of source line selection transistors does not prevent the voltage VERxe2x88x92 from reaching the transistor sources and creating an electrical field causing tearing off of charges trapped in the floating gates.
In view of the foregoing background, an object of the present invention is to provide a process for selective erasure of a page in a FLASH memory sector that does not require the use of source line selection transistors.
Another object of the invention is to provide a process for selective erasure of a page in a FLASH memory sector that is compatible with the channel erase method.
Another problem that this invention is intended to solve relates to xe2x80x9crefreshmentxe2x80x9d of the memory cells of a FLASH memory. In other words, deprogramming of cells in which the threshold voltage is modified. The provision of a FLASH memory erasable by page is only useful if the user is allowed to erase and reprogram the same page a large number of times without worrying about other memory pages. However, the memory cells of the other pages are directly connected to the bit lines BLi and are not protected by an access transistor as in the case of EEPROM memories. The memory cells will repeatedly receive on their drains the programming voltage applied to the cells of the page on which the user carries out erase and programming cycles, which will cause a gradual modification of electrical charges trapped in their floating gates, and will eventually cause data corruption.
One known approach to overcome this disadvantage is to provide a threshold voltage check for all transistors in the memory array after programming each word or after a number of word programming cycles. The check on the threshold voltage is followed by reprogramming programmed transistors for which the threshold voltage Vt is less than an authorized threshold. The disadvantage of this type of systematic checking process on the entire memory array is that it significantly slows down operation of the memory while occupying the microcontroller controlling the operation.
Thus, another purpose of this invention is to provide a process and a device in a FLASH memory for checking and reprogramming memory cells that is straightforward and efficient to use, and is transparent to the user.
These objectives are achieved by a process for recording data in a FLASH memory, including a step in which a memory page is erased and programmed, and a step in which the threshold voltage for programmed transistors is checked. Programmed transistors with a threshold voltage lower than a determined threshold may be reprogrammed, in which the checking and reprogramming step, if used, is applied to floating gate transistors for at least one page. The address of these transistors is read in a non-volatile counter formed by at least one row of floating gate transistors.
According to one embodiment, the counter is incremented by one unit after checking at least one page, by programming at least one floating gate transistor in the counter without erasing the other transistors in the counter. The transistor programmed in each new increment of the counter is the transistor following the transistor programmed in the previous increment according to a reading direction of the counter.
According to one embodiment, the counter comprises a plurality of words with increasing rank, and the address of the page to be checked is read in the counter in several steps. These steps include reading the counter word by word until finding a word containing a bit corresponding to an erased transistor, determining the high order bits of the address of the page to be checked using the rank of the first word containing a bit corresponding to an erased transistor in the counter, and determining the low order bits of the address of the page to be checked using the rank of the first bit corresponding to an erased transistor in the first word found.
According to one embodiment, the floating gate transistors encountered are laid out in a sector exclusively dedicated to the counter, such that programming voltages applied to floating gate transistors in another sector of the memory have no effect on the floating gate transistors used by the counter.
According to one embodiment, a page is checked word by word and the check of a word includes a first reading of the word by applying a first read voltage to the transistor gates corresponding to the word considered, and a second reading of the word by applying a second read voltage to the transistor gates corresponding to the word considered. The transistors are reprogrammed if the results of the two reads are not the same based upon the value of the word read when the first read voltage is applied as the reference value.
According to one embodiment, the process comprises a check of K pages after each time that a page is programmed. According to one embodiment, the process includes the check of only one page after programming Kxe2x80x2 pages.
According to one embodiment, erasing a page includes applying a positive erase voltage to the source or drain electrodes on all floating gate transistors in a memory sector including the page to be erased, applying a negative erase voltage to the gates of the transistors for the page to be erased, and applying a positive inhibit voltage to the transistor gates for at least one page that is not to be erased.
According to one embodiment, the process comprises providing voltage adaptor circuits in memory, with a page selection signal being applied to the input of these adaptor circuits. The adaptor circuits output the following data to the gates of the transistors for the corresponding page. A positive voltage is output when the selection signal is equal to a first value corresponding to non-selection of the page and the memory is in the erase mode, or when the selection signal has a second value corresponding to selection of the page and the memory is not in the erase mode, or a biasing voltage less than the positive voltage when the selection signal is equal to the second value and the memory is in the erase mode, or when the selection signal is equal to the first value and the memory is not in the erase mode.
According to one embodiment, the adaptor circuits are supplied with the following: while erasing a page a biasing voltage equal to the negative erase voltage and a positive voltage equal to the inhibit voltage is supplied, and while reading a word in memory a biasing voltage equal to the ground potential and a positive voltage equal to a read voltage is supplied.
This invention is also applicable to a FLASH memory erasable by page including a memory array including a plurality of floating gate transistors connected by their gates to word lines, with all transistors connected to a particular word line forming a page in the memory array. A set of pages forms a sector in the memory array. Checking means checks the threshold voltage of the floating gate transistors. Programmed transistors with a threshold voltage below a determined threshold are reprogrammed. The check means includes a non-volatile counter formed by at least one row of floating gate transistors, means of reading the address of at least one page to be checked in the counter, and means of incrementing the counter after checking at least one page.
According to one embodiment, the means for reading the address of at least one page to be checked include means for reading the counter word by word and searching for a word containing a bit corresponding to an erased transistor, means for outputting high order bits of the address of the page to be checked starting from the rank in the counter of the first word found containing a bit corresponding to an erased transistor, and means of calculating low order bits of the address of the page to be checked starting from the rank in the first word found of the first bit corresponding to an erased transistor.
According to one embodiment, the means for incrementing the counter are arranged to program at least one floating gate transistor in the counter without erasing the other transistors in the counter. The transistor programmed in each new increment is the transistor following the transistor programmed in the previous increment in the read direction of the counter.
According to one embodiment, the floating gate transistors in the counter are laid out in a sector exclusively dedicated to the counter, such that programming voltages applied to floating gate transistors in another memory sector do not have any effect on the floating gate transistors in the counter.
According to one embodiment, the means for checking a page include means for reading a word in the page by applying a first read voltage to the transistor gates corresponding to the word considered, reading the same word on the page by applying a second read voltage to the transistor gates corresponding to the word considered, comparing the results of these two reads, reprogramming the transistors if the results of the two reads are different, and using the value of the word read by applying the first read voltage as a reference value.
According to one embodiment, the memory comprises means such that when a page is erased, a positive erase voltage is applied to the source and drain electrodes of all floating gate transistors in the sector including a page to be erased, and a word line decoder connected to word lines in memory. This includes means for applying a negative erase voltage when a page is erased to the transistor gates for the page to be erased, while applying a positive inhibit voltage to the transistor gates for at least one page that is not to be erased.
According to one embodiment, the word line decoder comprises voltage adaptor circuits into which a page selection signal is input, and the following is output to the transistor gates for the corresponding page: a positive voltage when the selection signal is equal to a first value corresponding to non-selection of the page and the memory is in the erase mode, or when the selection signal has a second value corresponding to selection of the page and the memory is not in the erase mode, or a biasing voltage less than the positive voltage when the selection signal is equal to the second value and the memory is in the erase mode, or when the selection signal is equal to the first value and the memory is not in the erase mode.
According to one embodiment, the memory comprises means for providing the following to voltage adaptor circuits: when a page is being erased a biasing voltage equal to the negative erase voltage and a positive voltage equal to the inhibit voltage is provided, and while a word is being read in memory, a biasing voltage equal to the ground potential and a positive voltage equal to a read voltage is provided.
According to one embodiment, the voltage adaptor circuit comprises an output inverter stage, into which is first input the positive voltage and second the biasing voltage, and an inverter stage driver stage including a logical EXCLUSIVE OR function into which the selection signal is input and a signal with a first value when the memory is in the erase mode and a second value when the memory is not in the erase mode.
According to one embodiment, the positive erase voltage is applied to the source or drain electrodes of the floating gate transistors through the material forming the transistor channels.